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Systolic processor for implementation of antenna arrays adaptation algorithm
Last modified: 2014-07-01
Abstract
In this work synthesis of the systolic processor for rank-one modification of LDLT decomposition is realized. The synthesized systolic processor makes possible fast modification of LDLT factorization according Cholesky (at the rate of input sample arrival from adaptive array elements) and demonstrates the possibility of obtaining effective task solution schemes appearing in building up STSP devices.
Conference papers are not currently available.